As faster operation of computers has been sought, numerous hardware/firmware features have been employed to achieve that purpose. One widely incorporated feature directed to increasing the speed of operation is pipelining in which the various stages of execution of a series of consecutive machine level instructions are undertaken simultaneously. Thus, in a simple example, during a given time increment, a first stage of a fourth (in order of execution) instruction may be carried out while a second stage of a third instruction, a third stage of a second instruction and a fourth stage of a first instruction are all performed simultaneously.
Pipelining dramatically increases the apparent speed of operation of a computer system. However, it is well known that the processing of a transfer (sometimes called a branch) instruction when it is necessary to find a target (i.e., when the conditions calling for a transfer are met) temporarily slow down processing while the target instruction is found in the cache. Even when an instruction cache is provided, the target must be found and processed before it can be sent to the pipeline. It is to significantly speeding up the average rate of servicing transfer operations that the present invention is directed.